Hello,
based on your detailed description and our internal analysis, here's the explanation for the flickering issue:
Why Disabling D-Cache Reduces Flickering
We assume that when D-Cache is disabled, all CPU memory accesses go directly to SDRAM, which actually reduces the peak memory bandwidth demand. With D-Cache enabled, cache line fills and writebacks likely create burst memory traffic that can temporarily saturate the memory bus. During your screenshot operations, these cache-related memory bursts compete with the LTDC's continuous pixel data fetching, causing the display controller to miss its real-time requirements and resulting in the horizontal shifts/scrambling you observe.
The issue isn't cache coherency per se, but rather memory bandwidth contention between multiple bus masters (CPU with cache activity, DMA2D, LTDC) all competing for SDRAM access simultaneously.
Recommendation Based on Our STM32F769-Discovery Observations
Based on our analysis with the STM32F769-Discovery board, we observed that the default display configuration uses a frame rate of 65Hz with a pixel clock of 26MHz. We found that reducing the display frame rate from 65Hz to 60Hzand correspondingly lowering the pixel clock to approximately 23MHz successfully eliminated flickering during intensive memory operations.
We recommend checking if your display configuration uses similar parameters and testing with reduced frame rate and pixel clock settings. This approach reduces the LTDC's memory bandwidth requirements and provides more bandwidth headroom for other bus masters during operations like screenshot exports, while maintaining your D-Cache performance benefits.
Additional Recommendation to Avoid Concurrent Access of CPU and DMA2D
There is one function in ew_bsp_graphics.c that can be used to avoid parallel activities of DMA2D and CPU:
/*******************************************************************************
* FUNCTION:
* EwBspGraphicsConcurrentOperation
*
* DESCRIPTION:
* The function EwBspGraphicsConcurrentOperation configures the operation mode
* of DMA2D and CPU. If concurrent operation is enabled, the CPU will work in
* parallel while the DMA2D is transferring data. If concurrent operation is
* disabled, the CPU will wait everytime the DMA2D is active.
* This feature is intended to limit the memory bandwidth, e.g. during display
* update or other bandwidth consuming activities.
*
* ARGUMENTS:
* aEnable - flag to switch on/off concurrent operation mode.
*
* RETURN VALUE:
* None
*
*******************************************************************************/
void EwBspGraphicsConcurrentOperation( int aEnable )
This function could help to avoid the memory bandwidth issue in certain situations. However, the graphical performance will go down. This function can be used to avoid parallel activities of DMA2D and CPU while the screenshot is exported.
Usage recommendation: Call EwBspGraphicsConcurrentOperation(0) before starting the screenshot export operation and EwBspGraphicsConcurrentOperation(1) after completion to temporarily reduce memory bandwidth contention during critical operations.
Best regards,
Manfred.
