Hello Manfred,
I wouldn't focus too much on USB being affected by this issue. The same issue can be experienced on the SD/MMC interface.
Both issues occur if and only if double buffering is active, which most likely locates the root cause close to EmWi.
For sure, there might be a bug introduced by the modifications of the Platform Package that we had to implement in order for STM32F769 to support RGB interface, so it is important to us to understand the issue thorouhghly.
I think some blocking of CPU buses may need to be taken into account. There are multiple bus masters, like the core, the DMAs, the memory-mapped QSPI interface, and the DMA2D graphics accelerator, each of them competing for bus access.
These mechanisms can hardly be analyzed by conventional debuggers because they are transparently and invisibly handled by hardware.
We have learnt that the DMA2D accelerator can generate heavy bus load when reading frame buffer contents. Beyond the CPU cache, the DMA2D has a hardware FIFO that prefetches buffer data (if this fails, the infamous "data starvation" issue occurs). We have not found, however, a means to quantify DMA2D bus load. Can this be done by a calculation based on pixel clock?
There are not just interrupt priorities to be set, but there are also DMA priorities.
What are your recommendations of DMA priorities when QSPI is memory-mapped, reading graphics resources from serial flash, in parallel with DMA2D and others like SD/MMC DMA?
Thanks,
Steffen