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Hi All,

 I had been using the LPC54628 and a 7" LCD (Newhaven NHD-7.0-800480EF-ASXN#-CTP) successfully with Embedded Wizard. And now I am trying to get this same display working with EW's RT1060 Package and Display BSP. However, the RT1060 display bsp has changed a lot from the LPC. Specifically the clocking. Below are the #defines I had been using for the LPC bsp:

 

/* LPC DISPLAY BSP /////////////////////////
// Rocktech RK043FN02H-CT LCD
#define APP_LCD LCD
#define LCD_PANEL_CLK 9000000
#define LCD_HSW 2
#define LCD_HFP 8
#define LCD_HBP 43
#define LCD_VSW 10
#define LCD_VFP 4
#define LCD_VBP 12
#define APP_LCD_IRQHandler LCD_IRQHandler
#define APP_LCD_IRQn LCD_IRQn
*/

// Newhaven NHD-7.0-800480EF-ASXN#-CTP LCD
#define APP_LCD LCD
#define LCD_PANEL_CLK 30000000
#define LCD_HSW 48     // hsync pulse width?
#define LCD_HFP 40     // front porch
#define LCD_HBP 88     // back porch
#define LCD_VSW 3     // vsync pulse width
#define LCD_VFP 13     // front porch
#define LCD_VBP 32     // back porch
#define APP_LCD_IRQHandler LCD_IRQHandler
#define APP_LCD_IRQn LCD_IRQn

 

...and here are the default #defines for the RT1060 bsp:

// RT1060 BSP //////////////////////////////

// Rocktech RK043FN02H-CT LCD
#define LCD_HSW 41
#define LCD_HFP 4
#define LCD_HBP 8
#define LCD_VSW 10
#define LCD_VFP 4
#define LCD_VBP 2
#define LCD_POL_FLAGS \
    (kELCDIF_DataEnableActiveHigh | kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DriveDataOnRisingClkEdge)  
  
  
... which are for the same 4" Rocktech RK043FN02H-CT LCD that the LPC uses. What I don't understand is why they are so differant than the LPC #defines when it's the same dislay. This has me worried as I want to get the NewHaven LCD working. And #define LCD_PANEL_CLK is no longer a #define option on the RT1060...?! Please advise as to how I should get the above NewHaven clock, sync and porch etc settings setup correctly on RT1060. Thank you!

1 Answer

0 votes
by
Hi Mike,

the display controller of the RT1060 and LPC54628 is not the same and the defined parameters that you can see at the beginning of ew_bsp_display.c are just input parameters for the LCD controllers. How they are exactly working you should find in the documentation from NXP, then you probably find why the same named parameters differs to each other.

Your 7" Newhaven LCD  is already working with the LPC board, that’s great! I would recommend to copy theses parameters to the RT1060 to check out whether it works with it too. If it do not works correctly with the same parameters try to find out the necessary timings with the LCD's datasheet. In case that you do not have a datasheet for this display, I would recommend to change the timing parameters step by step until you find a setup that is working for the 7” display.

Kind regards

Tim
by
Tim, the display displays but with flicker because the clocking is wrong. I found out the necessary timings, I pasted them above. They come from the display's datasheet, as clocking, pulse widths, porches etc are associated with the display and not NXP's LCD controller internal to the iMXRT.

That undrestood now and put aside, the NewHaven is at 30mhz instead of 9mhz for the 4" Rocktech. However, I need guidance on getting that set in the EW BSP as there is no longer a #define for it...

...as Embedded Wizard's RT1060 BSP now has the code below instead of the #define for clocking. And, it being EW's BSP code, I'll need some guidance from EW.

void BOARD_InitLcdifPixelClock(void)
{

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
     */

   clock_video_pll_config_t config = {
           .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 0,
       };  
    CLOCK_InitVideoPll(&config);

...

}
by

Hi Mike,

 

The code that you see in this snippet is a part of the fsl_block.h and fsl_clock.c. This is an abstraction layer from NXP for easy adjusting the hardware modules like the clock.

We also copied this initialisation code from NXP examples to our build environment and didn’t adjust them by our own.

For setting up the new pixel clock NXP recommends the clock configuration tool which is integrated in MCUXpresso and also available online.

Link to documentation

 

Kind regards

 

Tim

 

by

Well, sure the clocking API is from NXP's codebase, and I've read up on the PLL config. But that implimentation in the BSP needs further explanation. Why does your comment say 93Mhz when the Rocktech display runs at 9.3Mhz. Why the factor of 10?

Here's your full comments:

    /*
     * The desired output frame rate is 60Hz. So the pixel clock frequency [for RockTech] is:
     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
     * Here set the LCDIF pixel clock to 9.3M.
     */

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
     */

 

Your first comment block spells out the math behind and goal of 9.3mhz. But then your PLL code states the goal is 93mhz. So why the factor of 10 increase?

by

Hi Mike,

 

both value are for different configurations:

LCDIF pixel clock = 9.2 M

Video PLL output clock = 93MHz

 

These lines are excatly the same as in the "elcdif_lut" sdk example and was not made by us.

 

Kind regards

 

Tim

by
I see... The BSP code was lifted line for line from NXP's example. Including the comments. I didn't realize that. I'll ask NXP for clarification.

Thanks again Tim!

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